VHDL tools VHDL tools
Contents: simulators, synthesis tools, FPGA synthesis, FPGA circuits, graphic interfaces 1, 2, rapid simulators, freeware tools
[modeltechnology | accolade| renoir| leonardo| xilinx | synopsys | cadence]
These pages collect some important links to leading EDA companies which offer modern synthesis tools, graphic interfaces and efficient simulators.
ModelTech simulator is one of most used VHDL/Verilog simulators. It includes the compilers (separate comiplers for VHDL and Verilog) and the simulator.
The tool maintains design libraries which are portable across different architectural/operational platforms (UNIX, Windows'95/NT,..)
The following are the images captured from the graphical interface offered by the ModelTech simulator.
ACCOLADEAccolade Design Automation's PeakVHDL simulator is a design entry and simulation system
that is intended to use the VHDL for advanced circuit design projects. The system includes
simulator, source code editor, hierarchy browser and on-line resources for VHDL users.
PeakVHDL cab used to create and manage new and existing VHDL projects. It can be
integrated in different electronic design environments.
A simplified demonstration version of ACCOLADE simulator may be downloaded from
www.ac-eda.com.
Renoir system provides a modern graphical entry to generate VHDL/Verilog synthesizable code from easy to use schematics including well-known forms like:
The modelers can generate powerfull and efficient synthesizable code in just a couple of hours
Mentor Graphics Renoir is a next generation HDL graphical entry tool that can generate Verilog and VHDL from Moore/ Mealy state, flow chart, truth table and block diagrams for FPGA, ASIC and IC. It is available on UNIX (SUN/ HP) and Windows NT/95 platforms. It includes interfaces to logic synthesis, digital simulation, HW-SW co-verification, requirements tools. VHDL and Verilog Intellectual Property (I.P.) is also supported.
Exemplar Logic Inc., a supplier of logic synthesis software for Windows and UNIX platforms, today announced that it is introducing a new synthesis design environment named Leonardo. Leonardo adds support for preservation and manipulation of hierarchical designs and interactive synthesis.
For the first time, Exemplar's users can interactively control synthesis, selectively optimizing different parts of their designs for speed or area. Users can change the design hierarchy, depending on their design needs. Leonardo facilitates "what-if" analysis, allowing users to try alternate scenarios without leaving the Leonardo design environment.
Robert Barker, Exemplar's vice-president of marketing, noted "Over the next few years, FPGA vendors will introduce devices with finer grain architectures, which push the 100K gate limits. These FPGAs require an ASIC-like design methodology that allows designers to design interactively with more control over their synthesis environment. Our roadmap follows this same path."
Exemplar Logic, the number one supplier of programmable logic synthesis software, and Xilinx, the world's largest supplier of programmable logic solutions, today announced that Exemplar's Leonardo synthesis solution is fully certified for the Xilinx XC4000EX family, with unique support for the XC4000EX family's SelectRAM Memory feature. There is a diagram showing the Xilinx flow with Leonardo.
Xilinx: leading FPGA company
The Future of FPGAs
A white paper by the company that invented them
Introduction
As programmable logic suppliers accelerate their use of advanced deep submicron technologies,
digital designers can expect to see higher densities and faster devices at lower voltages that
will be more competitive than ever with traditional ASICs. Within the next decade, Xilinx
believes that programmable logic will become one of the largest segments of the logic market,
surpassing both standard logic and masked gate arrays. This phenomenon will change how logic
is designed, making programmable logic pervasive in many engineering organizations. This white
paper examines a number of fundamental questions about the changes taking place with high
density programmable logic technology. And it examines how Xilinx, as the inventor of FPGAs
and the industry's leading innovator, is providing answers to those questions.
FPGAs: The New Process Drivers
New field programmable gate arrays (FPGAs) manufactured using advanced 0.35 and 0.25
micron technology and offering in excess of 100,000 logic gates will be widely available during
1997. In a shift that brings them to the forefront of progress in semiconductor manufacturing,
FPGAs today are becoming ideal vehicles for driving CMOS process technology development. It
is easier to quickly identify manufacturing process defects in FPGAs, which are standard
SRAM-based devices, than it is in, say, microprocessors. In addition, ever higher transistor
counts in FPGAs and their use of multiple metal interconnect layers truly stress a CMOS
process. For example, the new Xilinx XC4085XL FPGA, the industry's highest density device
scheduled for delivery during the first half of 1997, is fabricated on a 0.35 micron, three-layer
metal process. The XC4085XL has 16 million transistors, more than three times the number in
Intel's Pentium ProTM processor. As Xilinx makes the transition to 0.25 micron, five-layer metal
technology in the near future, the company plans to manufacture parts with more than 30
million transistors. Before the turn of the century, Xilinx will be using 0.18 micron technology
to build devices with 60 million transistors. Using FPGAs as process drivers ensures that design
engineers will have access to the largest and fastest devices that can be built using any
technology.
Xilinx SmartSearchXilinx SmartSearch provides the best Programmable Logic searching available anywhere. We're currently indexing over 50 different sites rich with programmable logic content. You can also constrain your search to focus on any one or more of the indexed sites. For the Xilinx site you can constrain your search to look only for general items such as application notes or datasheets, or search for topic areas such as PCI or DSP.
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Synopsys : leading high level synthesis company
Successful company which introduced efficient high level silicon compilers.
Synopsys COSSAP digital signal processing design system
Synopsys Design Compiler
Synopsys Behavioral Compiler
Synopsys' Behavioral Compiler(TM) is a high-level synthesis tool that allows designers to evaluate alternate architectures, then quickly create an optimal gate-level implementation. Behavioral Compiler creates designs that map to a flexible target architecture, which consists of a datapath, memory I/O, and a control FSM .
Behavioral code (VHDL/Verilog) => Automatic Architecture Creation (Control & Data Path) => Selection & Implementation.
FPGA evaluation
FREE! Download FPGA Express evaluation software today. Version 1.2 is now available with support for Altera, Lucent and Xilinx.
Synopsys Model Directory
Cadence: major EDA company
One of the fastest VHDL simulators
"Leapfrog uses a native compiled code approach which delivers performance unmatched by any other commercially available simulator. Leapfrog does not go through an intermediate "translation" step to C like other tools, instead leveraging the inherent concurrency of VHDL to reduce simulation time. The result is simulation performance that combines the fast set-up time of interpreted simulators with run-time performance that surpasses compiled code tools.
The single, high-speed engine for design analysis and design implementation makes Leapfrog the most efficient tool for all phases of VHDL-based design. Users benefit from the performance advantage of Leapfrog by reducing the amount of time they spend in simulation, allowing more opportunity to perform what-if analysis at the RTL/behavioral level.
Leapfrog's native compiled code technique is portable across hardware architectures and the simulator is available on leading UNIX-based workstation platforms from Sun, H-P and IBM.
The lack of certified ASIC libraries has hampered users of VHDL in the past. Leapfrog solves that problem through its Model Import package option. Users have access to more than 180 certified ASIC libraries that can be used directly in a VHDL environment with Leapfrog. Leapfrog interacts withVerilog-XL(tm) through a performance-oriented interlocking kernel approach, which is completely transparent to the user, to provide the most advanced language interoperability capability available today.
Users not only benefit from the wide range of ASIC libraries available to them through Verilog Model Import, but the environment provides a smooth mixed-level and gate-level solution, including the gate-level performance achieved with Cadence's "XL" algorithm. The designer remains in a native VHDL environment throughout the design process, even debugging Verilog models with the Leapfrog debugger, and can intermix VHDL and Verilog models in the flow. In addition, back-annotation of timing data is supported as are existing PLI applications"
pretty printing:
VHDL grammar and parsing:
Other tools: