STRUCTURED LOGIC DESIGN WITH VHDL

STRUCTURED LOGIC DESIGN WITH VHDL
Author: Nikola Jevtović Computer Science Department School of Electrical Engineering University of Belgrade

Reference: “Structured Logic Design With VHDL”
James R. Armstrong, F. Gail Gray Virginia Tech Structured Logic Design with VHDL

Structured Design Concepts
Chapter 1 Structured Design Concepts Structured Logic Design with VHDL

The abstraction hierarchy can be expressed in two domains: Structural domain: A domain in which a component is described in terms of interconnection of more primitive components. Behavioral domain: A domain in which a component is described by defining its I/O response. Structured Logic Design with VHDL

Level of detail commonly used in design Level of Detail Behavioral Domain Representation Structural Domain Primitives System Performance specifications Computer, disk unit, radar Chip Algorithm Microprocessor, RAM, ROM, UART, parallel port Register Data flow Register, ALU,COUNTER, MUX, ROM Gate Boolean equations AND, OR, XOR, FF Circuit Differential equations Transistor, R, L, C Layout/Silicon None Geometrical shapes Structured Logic Design with VHDL

Silicon level Circuit level Gate level Structured Logic Design with VHDL

Register level Chip level System level Structured Logic Design with VHDL

Textual vs. Pictorial Representations Example of pictorial representations of logical circuits X state S0 S1 S2 S1/0 S1/1 1 S2/0 s2/0 S2/1 state code y1y0 S0 S1 S2 00 01 11 State Table State Assignment …also timing diagrams and/or truth tables (K-maps). Structured Logic Design with VHDL

Textual vs. Pictorial Representations Common textual methods are: natural language (e.g. English), equations (Boolean or differential) and computer languages (hardware description language -HDL) Text is better for representing complex behavior; pictures are better for illustrating interrelationships. Structured Logic Design with VHDL

Types of behavioral descriptions Algorithmic : the procedure defining the I/O response is not meant to imply any particular physical implementation. Data flow : the data dependencies in the description match those in real implementation. Both are HDL implementations of behavior at the register and chip levels. Structured Logic Design with VHDL

Design process Logic synthesis Natural language (System level) Logic (Gate level) Natural language synthesis Algorithmic (Chip level) Circuit (Circuit level) Layout synthesis Algorithmic synthesis Data Flow (Register level) Geometrical Shapes (Layout level) Structured Logic Design with VHDL

Structural design decomposition Top-down design Bottom-up design Partial tree design Full tree design Behavioral modeling Structured Logic Design with VHDL

Structured Logic Design with VHDL
Chapter 2 Design Tools Structured Logic Design with VHDL

Design Tools Editors (textual or graphic) Simulators (stochastic or deterministic) Checkers and Analyzers Optimizers and Synthesizers Structured Logic Design with VHDL

Design Tools Schematic editor : An editor which can be used to create and display an interconnected set of graphic tokens. It has following features: A library of primitive symbols. A system of graphic windows (used to create an interconnect of graphic tokens). Commands for creating wirelists. Structured Logic Design with VHDL

Design Tools Simulator : A program which models the response of a system stimuli. Process : A computational entity which models the function and delay of the digital device. process (CLK,R) begin if R=‘0’ then Q <= ‘0’; elsif CLK’EVENT and CLK=‘1’ then Q <= D; end if; end process; Graphical representation R D CLK Q D Q R D CLK Q Digital device VHDL process Structured Logic Design with VHDL

Chapter 3 Basic Features of VHDL Structured Logic Design with VHDL

Basic Features of VHDL A basic element of a VHDL description is the block. architecture BLOCK_STRUCTURED ----- Outer Block Declaration Section begin Outer Block Executable Statements A: block --- Inner Block A Declaration Section Inner Block A Executable Statements end block A; end BLOCK_STRUCTURED; Structured Logic Design with VHDL

Basic Features of VHDL Lexical description Character Set: Upper case letters: A … Z Digits: 0 … 9 Special characters: “ # & ‘ ( ) * + , - . / : ; < = > _ | Space character: (20) Format effectors: Carriage return: (0D) Line feed: (0A) Form feed: (0C) Horizontal tabulation: (09) Vertical tabulation: (0B) Lower case letters: a… z Other special characters: ! $ ? [ \ ] ^ ` { } ~ Structured Logic Design with VHDL

Basic Features of VHDL Delimiters – characters that are used to separate lexical elements and have specific meanings in the language: & ‘ ( ) * + , / : ; < = > | Compound delimiter is a sequence of two delimiters that have special meanings: => ** := /= >= <= <> -- Structured Logic Design with VHDL

Basic Features of VHDL Reserved words abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant downto disconnect else elsif end entity exit file function for generate generic guarded if in inout is label library linkage loop map mod nand new next nor not null of on open or others out port package process procedure range record register rem report return select severity signal subtype then to type transport units until use variable wait when while with xor Structured Logic Design with VHDL

Basic Features of VHDL Classification of Data Types: Scalar (their values are single entities) Enumeration – discrete Integer – discrete, numeric Physical – numeric Floating point (or real – numeric) Composite (their values are complex objects) Array – all elements have the same type Record – elements may have different types Access (provide access to other types) File (provide access to other files) Structured Logic Design with VHDL

Basic Features of VHDL Classes of Objects Constant – An object whose value is specified at compile and cannot be changed during simulation. Variable – A data object whose current value can be changed by VHDL statements. Signal – A data object that has a time dimension. Using waveforms, future values can be assigned without affecting the current value. Structured Logic Design with VHDL

Basic Features of VHDL Declaration of Data Objects Declaration of Constants constant const_name:type_name:=const_value; Declaration of Variables variable var_name:type_name:=init_value; Declaration of Signals signal sig_name:type_name:=init_value; Structured Logic Design with VHDL

Basic Features of VHDL Assignment Statements
A Variable Assignment Statement A variable instantaneously replace its current value by a new value: var_name := new_var_value; A Signal Assignment Statement A new value of a signal is scheduled to occur at some future time. The current value is never changed: sig_name<=‘sig_value’ after int_value ns; If not specified, the default value of time is delta time (infinitesimally small value of time in the future). Structured Logic Design with VHDL

Basic Features of VHDL Operators in VHDL Logical: and or nand nor xor Relational: = /= < <= > => Adding: + - & Signing: + - Multiplying: * / mod rem Miscellaneous: ** abs not lowest priority highest Structured Logic Design with VHDL

Basic Features of VHDL Sequential Control Statements Wait statement wait on object until expression for int ns; wait on X,Y until Z=0 for 100ns; wait for 100ns; wait on A,B,C; wait on A,B,C for 100ns; wait until Z=0; wait on X,Y until Z=0; Structured Logic Design with VHDL

Basic Features of VHDL Sequential Control Statements If Statement if {condition1} then {sequence_of_statements_1} elsif {condition2} then {sequence_of_statements_2} … else {sequence_of_statements_n} end if; if A < 0 then LEVEL := 1; elsif A > 10 then LEVEL := 3; else LEVEL := 2; end if; Structured Logic Design with VHDL

Basic Features of VHDL Sequential Control Statements Case Statement case {expression} is when {choices_1} => {sequence_of_statements_1} when {choices_2} => {sequence_of_statements_2} … when others => {sequence_of_statements_n} end case; case A+B is when 0 => X <= “ZERO”; when (1 to 20) => X <= “POSITIVE”; when others => X <= “NEGATIVE”; end case; Structured Logic Design with VHDL

Basic Features of VHDL Sequential Control Statements Loop Statement -- FOR loop for NAME in {range} loop {sequence_of_statements} end loop; for I in 1 to 10 loop A(I) := A(I) + 1; end loop; -- WHILE loop while {condition} loop {sequence_of_statements} end loop; while A<B loop A := A=1; end loop; -- Simple loop loop {sequence_of_statements} end loop; loop compute (x); exit when x<10; end loop; Structured Logic Design with VHDL

Basic Features of VHDL Sequential Control Statements Next Statement next {loop_label} [when condition] Exit Statement exit {loop_label} [when condition] Null Statement Does nothing, but it’s mandatory in “case” statements if no action is desired for certain choices – because all choices must be covered! Structured Logic Design with VHDL

component instantiation
Basic Features of VHDL Concurrent Statements -NOT executed in the order written; only when signal that affect the value computed by the statement changes; -Plus, executed once at the beginning of simulation; Some statement types are both concurrent and sequential; Sequential Concurrent assertion signal assignment procedure call if … then … case loop wait null next exit return process block component instantiation generate Structured Logic Design with VHDL

Basic Features of VHDL Concurrent Statements Process Statement LABEL: LABEL: process (sensitivity_signal_list) {constant_declarations} {var_declarations} begin {sequential_statements} end process LABEL; (sensitivity_signal_list) Fundamental statement type; All other concurrent statements can be written as processes; Label and sensitivity list are optional; Executed once at the beginning of simulation and when any signal in sensitivity list changes; Structured Logic Design with VHDL

Basic Features of VHDL Concurrent Statements Process Statement If there is no sensitivity list, process will execute once at the beginning of the simulation and thereafter whenever any signal in wait statement changes; There must be a wait statement to prevent an infinite loop. NO_LIST: process {constant_declarations} {var_declarations} begin {sequential_statements} wait on S1, S2 end process NO_LIST; wait on S1, S2 Structured Logic Design with VHDL

Basic Features of VHDL Concurrent Statements Concurrent Assert Statement If BOOL_EXPR is false then Message_string is written to the output device. LABEL: assert BOOL_EXPR report “Message_string” severity SEVERITY_LEVEL; LABEL: process (A, B, C) begin assert (A or B) = C report ”...” severity WARNING; end process LABEL; LABEL: assert (A or B)=C report “C is NOT equal to (A or B)” severity WARNING; equal Structured Logic Design with VHDL

Basic Features of VHDL Concurrent Statements Concurrent Signal Assignment Statement Executed: once at the beginning of the simulation; at any time any right side signal experiences an event. equal LABEL: C <= A or B; LABEL: process (A, B) begin C <= A or B; end process LABEL; Structured Logic Design with VHDL

Basic Features of VHDL Concurrent Statements Concurrent Signal Assignment Statement can be conditional. Executed: once at the beginning of the simulation; when any signal in any WAVFRM or any signal in any COND experiences an event. LABEL: SIGNAL_NAME <= [transport] WAVFRM1 when COND1 else WAVFRM2 when COND2 else ... WAVFRMn when CONDn else WAVFRMq; L1: S <= A or B when XX=1 else A and B when XX=2 else A xor B; Structured Logic Design with VHDL

Basic Features of VHDL Functions can be declared by specifying: the name of the function; the input parameters (if any); the type of the returned value; any declarations required by the function itself; an algorithm for the computation of the returned value. Structured Logic Design with VHDL

Basic Features of VHDL entity PULSE_GEN is generic (N: INTEGER; PER: TIME); port (START: in BIT; PGOUT: out BIT_VECTOR(N-1 downto 0); SYNC: inout BIT); end PULSE_GEN; architecture ALG of PULSE_GEN is function INT_TO_BIN (INPUT: INTEGER; N: POSITIVE) return BIT_VECTOR is variable FOUT: BIT_VECTOR(0 to N-1); variable TEMP_A: INTEGER:=0; variable TEMP_B: INTEGER:=0; begin TEMP_A:= INPUT; for I in N-1 downto 0 loop TEMP_B:= TEMP_A/(2**I); TEMP_A:= TEMP_A rem (2**I); if (TEMP_B = 1) then FOUT(N-1-I) := ‘1’; else FOUT(N-1-I) := ‘0’; end if; end loop; return FOUT; end INT_TO_BIN; begin process (START,SYNC) variable CNT: INTEGER :=0; if START’EVENT and START=‘1’ then CNT := 2**N-1; end if; PGOUT <= INT_TO_BIN (CNT,N) after PER; if CNT /= -1 and START = ‘1’ then SYNC <= not SYNC after PER; CNT := CNT-1; end process; end ALG; Function to convert an INTEGER type to type BIT_VECTOR (fig. 3.25) Structured Logic Design with VHDL

Basic Features of VHDL Procedures can be declared by specifying: the name of the procedure; the input and output parameters; any declarations required by the procedure itself; an algorithm. Structured Logic Design with VHDL

Basic Features of VHDL Procedure to add entities of type BIT_VECTOR procedure ADD (A,B: in BIT_VECTOR; CIN: in BIT; SUM: out BIT_VECTOR; COUT: out BIT) is variable SUMV,AV,BV: BIT_VECTOR (A’LENGTH-1 downto 0); variable CARRY: BIT; begin AV := A; BV := B; CARRY := CIN; for I in 0 to SUMV’HIGH loop SUMV(I) := AV(I) xor BV(I) xor CARRY; CARRY := (AV(I) and BV(I)) or (AV(I) and CARRY) or (BV(I) and CARRY); end loop; COUT := CARRY; SUM := SUMV; end ADD; (fig. 3.26) Structured Logic Design with VHDL

Basic Features of VHDL Subprogram Usage Rules For procedures: modes for parameters : in, out, inout ; object classes for parameters : constant, variable, signal ; if the mode is in and no object class is specified, constant is assumed; if the mode is inout or out and if no object class is specified, variable is assumed. Structured Logic Design with VHDL

Basic Features of VHDL Subprogram Usage Rules For functions: the only allowable mode for parameters is in ; the only allowable object classes are constant or signal ; if the object class is not specified, constant is assumed. Structured Logic Design with VHDL

Basic Features of VHDL Packages Use them to hold frequently used declarations; VHDL defines a STANDARD package; Visible by referring to the package name; Package body is not required if a package contains no subprograms; Access to the package is given by the use clause. Structured Logic Design with VHDL

Basic Features of VHDL Packages Definition of a package: package HANDY is subtype BITVECT3 is BIT_VECTOR(0 to 2); function MAJ3 (X: BIT) return BIT; end HANDY; Entity LOGSYS “sees” all the declarations from HANDY package: use work.HANDY.all; entity LOGSYS is port (X: in BITVECT3); end LOGSYS; Structured Logic Design with VHDL

Basic Features of VHDL Visibility Region: A logical continuous portion of a text. Declaration region: A region in which a name can be used to unambiguously refer to a declared entity. Once an entity has been declared in the declaration region, its name is visible to the end of that region. Two types of visibility: directly, within the region where entity is declared; by selection, through use and library clauses. Structured Logic Design with VHDL

Basic Features of VHDL Libraries When VHDL models are analyzed with no errors, the result is stored in a library. Libraries allow the existing VHDL models to be used in future VHDL descriptions Two types of libraries: work library, where current analysis results are stored resource libraries, referenced during analysis and simulation but cannot be written into Structured Logic Design with VHDL

Basic Features of VHDL Libraries contain primary and secondary units. Primary units are: entity; package; configuration declarations. Secondary units are: architectures; package bodies. they have logical and physical names. Logical name is: used in VHDL description; portable. Physical name is: used by the host OS to refer to the library; -system dependent. Structured Logic Design with VHDL

Basic Features of VHDL Configurations VHDL structural architectures are developed by specifying the interconnect between component models that are first declared and then instantiated; Each instantiated component must be bound to a component model if it is to be simulated. VHDL Structural Model Design Library model pointers library models Configuration specification statement: for INSTANTIATED_COMPONENT use LIBRARY_COMPONENT; (fig. 3.29) Structured Logic Design with VHDL

Basic Features of VHDL entity TWO_CONSECUTIVE is port (CLK,R,X: in BIT;Z: out BIT); end TWO_CONSECUTIVE; use work.all; architecture STRUCTURAL of TWO_CONSECUTIVE is signal Y0,Y1,A0,A1: BIT:=‘0’; signal NY0,NX: BIT:=‘1’; component EDGE_TRIGGERED_D port (CLK,D,NCLR: in BIT;Q,QN: out BIT); end component; for all: EDGE_TRIGGERED_D use entity EDGE_TRIG_D (BEHAVIOR); component INVG port (I: in BIT; O: out BIT); for all: INVG use entity INV (BEHAVIOR); component AND3G port (I1,I2,I3: in BIT;O: out BIT); for all: AND3G use entity AND3(BEHAVIOR); component OR2G port (i1,I2: in BIT;O: out BIT); for all: OR2G use entity (OR2(BEHAVIOR): begin C1: EDGE_TRIGGERED_D port map (CLK,X,R,Y0,NY0); C2: EDGE_TRIGGERED_D port map(CLK,ONE,R,Y1,open); C3: INVG port map (X,NX); C4: AND3G port map (X,Y0,Y1,A0); C5: AND3G port map (NY0,Y1,NX,A1); C6: OR2G port map (A0,A1,Z); end STRUCTURAL; Configuration specification for entity TWO_CONSECUTIVE (fig. 3.30) Structured Logic Design with VHDL

Basic Features of VHDL Configurations Another approach to binding components is through the use of component declarations. Remove all configuration specification statements (model pointers) from architecture and collect them in a configuration declaration. configuration PARTS of TWO_CONSECUTIVE is for STRUCTURAL for all: EDGE_TRIGGERED_D use entity work.EDGE_TRIG_D(BEHAVIOR); end for; for all: INVG use entity work.INV(BEHAVIOR); for all: AND3G use entity work.AND3(BEHAVIOR); end for; for all: OR2G use entity work.OR2(BEHAVIOR); end PARTS; (fig.3.31) Structured Logic Design with VHDL

Basic Features of VHDL File I/O Crucial requirement in VHDL is driving a model with test vectors. Related problems: initialize memories from external file; write simulation results to external file. Two types of files in VHDL: formatted; text. Files can be of mode in or out, but not inout ! Structured Logic Design with VHDL

Basic Features of VHDL – formatted type – File I/O Two declarations are required: a file type declaration; a declaration of the file itself. You cannot write to and read from the same host file during a given simulation – either in or out ! input file type INP_COMB is file of BIT_VECTOR; output file file OUTVECT: INP_COMB is out “TEST.VEC”; WRITE (OUTVECT: out INP_COMB; V: in BIT_VECTOR); file INVECT: INP_COMB is in “TEST.VEC”; loop exit when ENDFILE (INVECT); READ (INVECT, V, LENGTH); end loop; Structured Logic Design with VHDL

Basic Features of VHDL File I/O Unlike formatted files, text files are human readable. Create them by a text editor or some programming language output. You must use TEXTIO package which begins with: type LINE is access STRING; -- points to memory locations type TEXT is file of STRING; --input data in the host file For e.g.: file INVECT: TEXT is “TVECT.TEXT”; --declaration of TEXT file READLINE (INVECT,VLINE); --reading a single line from file READ (VLINE,V); -- reading single bit vector from line – text type – Structured Logic Design with VHDL

Basic VHDL Modeling Techniques
Chapter 4 Basic VHDL Modeling Techniques Structured Logic Design with VHDL

Propagation Delay Electronic signals must obey the laws of physics! There is always a finite delay between the time that a gate input changes value and the time that a gate output changes. The notation <= indicates a signal change that will occur after a propagation delay. The notation := indicates instantaneous variable assignment. Structured Logic Design with VHDL

Propagation Delay Delayed signal assignment AS <= X*Y after 2ns; BS <= AS+Z after 2ns; Instantaneous variable assignment AV := X*Y; BV := AV+Z; Initial t1 t1+2 t1+4 t1+6 X 1 4 5 3 Y 2 AS 8 10 15 Z BS 12 Initial t1 t1+2 t1+4 t1+6 X 1 4 5 3 Y 2 AV 8 10 15 6 Z BV 11 12 17 (fig. 4.1) Structured Logic Design with VHDL

entity STATEMENTS is port (X,Y,Z: in INTEGER; B: out INTEGER); end STATEMENTS; -- note: entity ports are always signals architecture PROP_DELAY of STATEMENTS is signal AS: INTEGER; begin process (X,Y,Z) AS <= X*Y after 2ns; B <= AS+Z after 2ns; end process; end PROP_DELAY; architecture INSTANTANEOUS of STATEMENTS is variable AV,BV: INTEGER; AV := X*Y; BV := AV+Z; B <= BV; end INSTANTANEOUS; Propagation Delay Complete code for instantaneous and delayed assignment statements (fig. 4.2) Structured Logic Design with VHDL

Delay and Concurrency Logic signals flow in parallel. Logic blocks 1 and 2 are activated simultaneously. Logic block 3 is activated as soon as Z1 or Z2 changes. Logic Block 1 Input Set 1 Z1 Logic Block 3 Output Z2 Logic Block 2 Input Set 2 (fig. 4.3) Structured Logic Design with VHDL

Delay and Concurrency Default propagation time is called delta delay. Delta is greater than zero but smaller then any other positive time. Example: two statements with delta delay AS <= X*Y; BS <= AS+Z; Initial t1 t1+delta t1+2*delta X 1 4 Y 2 AS 8 Z 3 BS 5 11 (fig. 4.5) Structured Logic Design with VHDL

Sequential and Concurrent Statements Two simple rules to determine type of statements: concurrent – if they are within architecture; sequential – if they are within process or subprogram. entity STATEMENTS is port (X,Y,Z:in INTEGER; BS:out INTEGER); end STATEMENTS; architecture SEQUENTIAL of STATEMENTS is begin process( X,Y,Z) variable AV,BV: INTEGER; AV := X*Y; BV := AV+Z; BS <= BV; end process; end SEQUENTIAL; architecture CONCURRENT of STATEMENTS is signal AS: INTEGER; begin AS <= X*Y; BS <= AS+Z; end CONCURRENT; (fig. 4.6) Structured Logic Design with VHDL

Implementation of Time Delay in Simulator Time delay can be specified in two ways: Y <= X; -- delta delay Y <= X after 10 ns; -- standard time until delay. During simulation the elapsed time in standard time units is called simulation time. There may be many simulation cycles associated with the same simulation time! No number of delta delays added together can cause simulation time to advance. Structured Logic Design with VHDL

Implementation of Time Delay in Simulator entity BUFF is port (X: in BIT; Z: out BIT); end BUFF; t=1ns t=4ns X architecture ONE of BUFF is begin process (X) variable Y1: BIT; Y1 := X; Z <= Y1 after 1ns; end process; end ONE; architecture THREE of BUFF is signal Y3: BIT; begin Y3 := X; Z <= Y3 after 1ns; end THREE; architecture FOUR of BUFF is signal Y4: BIT; begin Y4 <= X after 1ns; Z <= Y4 after 1ns; end FOUR; architecture TWO of BUFF is signal Y2: BIT; begin Y2 := X; Z <= Y2; end TWO; (fig. 4.8) Structured Logic Design with VHDL

Implementation of Time Delay in Simulator Time (ns) X Z1 Y2 Z2 Y3 Z3 Y4 Z4 ‘0’ +1 --- 1 ‘1’ +2 2 3 4 5 6 (fig. 4.9) Structured Logic Design with VHDL

Implementation of Time Delay in Simulator Time (ns) X Y5 Z5 Y5A Z5A ‘0’ +1 --- 1 ‘1’ +2 2 3 4 5 6 architecture FIVE of BUFF is signal Y5: BIT; begin process (X) Y5 <= X; Z <= Y5; end process; end FIVE; architecture FIVE_A of BUFF is process (X,Y5) end FIVE_A; (fig. 4.10) (fig. 4.11) Structured Logic Design with VHDL

Inertial and Transport Delay Example: Z <= I after 10 ns; --inertial delay Z <= transport I after 10ns; --transport delay Inertial delay: the signal propagation will take place if and only if an input persists at a given level for a specified amount of time. Transport delay: all changes of a signal will propagate regardless of how long changes stay at the new level. Inertial delay mechanism filters out inputs that change too rapidly. Structured Logic Design with VHDL

The VHDL Scheduling Algorithm Two concepts that implement delay are transactions and waveforms. Transaction is a pair consisting of a value and time: value is the future value of signal driver; time is the time at which the value becomes the current value of the driver. Waveform - a series of transactions ordered by time. Structured Logic Design with VHDL

The VHDL Scheduling Algorithm F DaZ DbZ Z I; process A J; process B Example: - signal Z is driven from two processes - DaZ and DbZ are drivers - F is resolution function 1 42ns 31ns 22ns 15ns 10ns CV transaction waveform DaZ Z (fig. 4.12) Structured Logic Design with VHDL

The VHDL Scheduling Algorithm Z I after 10ns I 1 2 t=0 t=5 I 1 2 t=0 t=10 3 t=16 1) Z 1 10ns 1) Z 1 10ns 2) Z 1 15ns 10ns transport 2) Z 1 3) Z 26ns 1 3) Z 15ns inertial (fig. 4.14) Structured Logic Design with VHDL

The VHDL Scheduling Algorithm Inertial delay has side effects, for e.g.: process begin Z <= ‘1’ after 50 ns; Z <= ‘0’ after 100 ns; wait; end process; If the initial value of Z is 0, the inertial delay rule will eliminate the (50ns, 1) transaction. There are two solutions: process begin Z <= transport ‘1’ after 50 ns; Z <= transport ‘0’ after 100 ns; wait; end process; process begin Z <= ‘1’ after 50 ns, ‘0’ after 100 ns; wait; end process; Structured Logic Design with VHDL

Modeling Combinational and Sequential Logic DEL X Z Basic Combinational Logic process (X) --declare process variables variable ZVAR: BIT; begin --represent circuit functionality --compute ZVAR Z <= ZVAR after DEL; --model circuit delay end process; Structured Logic Design with VHDL

Modeling Combinational and Sequential Logic DEL X Z Basic Sequential Logic Y process (X) --declare process variables variable YVAR, ZVAR: BIT; begin --represent circuit functionality --compute ZVAR Y <= YVAR after DEL; --state variable delay Z <= ZVAR after DEL; --output delay end process; Structured Logic Design with VHDL

Combinational Logic Gates Buffers Adders Multiplexers Decoders Encoders Shifters Structured Logic Design with VHDL

Combinational Logic Gate Primitive entity AND2 is generic (DEL: TIME); port (I1,I2: in BIT; O: out BIT); end AND2; architecture DF of AND2 is begin ) <= I1 and I2 after DEL; end DF; (fig. 4.18) The most basic of the combinational logic primitives Structured Logic Design with VHDL

Combinational Logic Buffer Primitive entity BUF is generic (DATA_DEL, Z_DEL: TIME); port (I,EN: in BIT; O: out BIT); end BUF; architecture ALG of BUF is begin process (I,EN) if EN = ‘1’ then O <= I after DATA_DEL; else O <= ‘1’ after Z_DEL; end if; end process; end ALG; Copy input I to output O when E=1. If E=0 then O will go to a high impedance condition. (in this case, highZ=1) (fig. 4.19) Structured Logic Design with VHDL

Combinational Logic Adder Primitive entity FULL_ADDER is generic (SUM_DEL,CARRY_DEL:TIME); port (A,B,CI: in BIT; SUM,COUT: out BIT); end FULL_ADDER; architecture DF of FULL_ADDER is begin SUM <= A xor B xor CI after SUM_DEL; COUT<= (A and B) or (A and CI) or (B and CI) after CARRY_DEL; end DF; Full 1-bit adder Inputs: two data bits and carry Outputs: sum and carry (fig. 4.20) Structured Logic Design with VHDL

Combinational Logic Multiplexer Primitive entity FOUR_TO_1_MUX is generic (DEL: TIME); port ( IN0,IN1,IN2,IN3: in BIT_VECTOR (3 downto 0); SEL: in BIT_VECTOR (1 downto 0); O: out BIT_VECTOR (3 downto 0)); end FOUR_TO_1_MUX; architecture DF of FOUR_TO_1_MUX is begin O <= IN0 after DEL when SEL = “00” else IN1 after DEL when SEL = “01” else IN2 after DEL when SEL = “10” else IN3 after DEL; end DF; (fig. 4.22) Multiplexer is a selector from a number of data sources. Generally, 2ⁿ to 1 multiplexer. In this case: n=4 . Structured Logic Design with VHDL

Combinational Logic Decoder Primitive entity TWO_TO_4_DEC is generic (DEL: TIME); port ( I: BIT_VECTOR (1 downto 0); O: out BIT_VECTOR (3 downto 0)); end TWO_TO_4_DEC; architecture ALG of TWO_TO_4_DEC is begin process (I) case I is when “00” => O<= “0001” after DEL; when “01” => O<= “0010” after DEL; when “10” => O<= “0100” after DEL; when “11” => O<= “1000” after DEL; end case; end process; end ALG; N-bit input activates one of 2ⁿ outputs. Decoder functions as a binary to decimal converter (fig. 4.23) Structured Logic Design with VHDL

Combinational Logic Encoder Primitive entity FOUR_TO_2_ENC is generic (DEL: TIME); port ( I: BIT_VECTOR (3 downto); O: out BIT_VECTOR (1 downto 0)); end FOUR_TO_2_ENC; architecture FOUR_TO_2_ENC is begin O <= “00” after DEL when I(0) = ‘1’ else “01” after DEL when I(1) = ‘1’ else “10” after DEL when I(2) = ‘1’ else “11” after DEL; end DF; (fig. 4.24) Encoders perform inverse function of decoders. Priority ranking is necessary for the inputs. Structured Logic Design with VHDL

Combinational Logic Shifter Primitive entity SHIFTER is generic (DEL: TIME); port ( DATA_IN: in BIT_VECTOR (3 downto 0); SR,SL: in BIT; IL,IR: in BIT; DATA_OUT: out BIT_VECTOR (3 downto 0)); end SHIFTER; architecture ALG of SHIFTER is begin process (SR,SL,DATA_IN,IL,IR) variable CON: BIT_VECTOR (0 to 1); CON := SR&SL; case CON is when “00” => DATA_OUT <= DATA_IN after DEL; when “01” => DATA_OUT <= DATA_IN(2 downto 0)& IL after DEL; when “10” => DATA_OUT <= IR & DATA_IN(3 downto1) after DEL; when “11” => DATA_OUT <= DATA_IN after DEL; end case; end process; end ALG; Shift right is division by 2, shift left is multiplication by 2. (fig. 4.25) Structured Logic Design with VHDL

Combinational Logic The Data Operations Package Structured Logic Design with VHDL

Structured Logic Design with VHDL

Sequential Logic Flip-flops Registers Latches Counters Memories Structured Logic Design with VHDL

Sequential Logic - Flip-flop Primitives entity JKFF is generic (SRDEL, CLKDEL: TIME); port ( S,R,J,K,CLK: in BIT; Q,QN: inout BIT); end JKFF; architecture ALG of JKFF is begin process (CLK,S,R) if S =‘1’ and R =‘0’ then Q <=‘1’ after SRDEL; QN<=‘0’ after SRDEL; elsif S=‘0’ and R=‘1’ then Q <=‘0’ after SRDEL; QN<=‘1’ after SRDEL; elsif CLK’EVENT and CLK=‘1’ and S=‘0’ and R=‘0’ then if J=‘1’ and K=‘0’ then Q <=‘1’ after CLKDEL; QN<=‘0’ after CLKDEL; elsif J=‘0’ and K=‘1’ then Q <=‘0’ after CLKDEL; QN<=‘1’ after CLKDEL; elsif J=‘1’ and K=‘1’ then Q <= not Q after CLKDEL; QN<= not QN after CLKDEL; end if; end process; end ALG; JK flip-flop model (fig. 4.32) Structured Logic Design with VHDL

Sequential Logic - Register Primitives entity REG is generic (DEL: TIME); port ( RESET,LOAD,CLK: in BIT; DATA_IN: in BIT_VECTOR(3 downto 0); Q: inout BIT_VECTOR(3 downto 0)); end REG; architecture DF of REG is begin REG: block (not CLK’STABLE and CLK=‘1’) Q <= guarded “0000” after DEL when RESET = ‘1’ else DATA_IN after DEL when LOAD = ‘1’ else Q; end block REG; end DF; Use registers to store data words. In our model both reset and load functions are synchronous but reset is having priority. (fig. 4.33) Structured Logic Design with VHDL

Sequential Logic - Latch Primitives entity LATCH is generic (LATCH_DEL:TIME); port ( D: in BIT_VECTOR (7 downto 0); CLK: in BIT; LOUT: out BIT_VECTOR(7 downto 0)); end LATCH; architecture DFLOW of LATCH is begin LATCH: block (CLK = ‘1’) LOUT <= guarded D after LATCH_DEL; end block LATCH; end DFLOW; CLK=‘1’ the output follows the input. CLK=‘0’ the output stores value. (fig. 4.34) Structured Logic Design with VHDL

Sequential Logic - Shift Register Primitive entity SHIFTREG is generic (DEL:TIME); port ( DATA_IN: in BIT_VECTOR (3 downto 0); CLK,LOAD,SR,SL: in BIT; IL,IR: in BIT; Q: inout BIT_VECTOR (3 downto 0)); end SHIFTREG; architecture DF of SHIFTREG is begin SH: block (not CLK’STABLE and CLK=‘1’) Q<= guarded DATA_IN after DEL when LOAD=‘1’ else Q(2 downto 0) & IL after DEL when SL=‘1’ and SR=‘0’ else IR & Q(3 downto 1) after DEL when SL=‘0’ and SR=‘1’ else Q; end block SH; end DF; Shift register is sequential, shifter is combinational! (fig. 4.36) Structured Logic Design with VHDL

Sequential Logic - Counter Primitive entity COUNTER is generic (DEL:TIME); port ( RESET,LOAD,COUNT,UP,CLK: in BIT;DATA_IN: in BIT_VECTOR(3 downto 0); CNT: inout BIT_VECTOR(3 downto 0)); end COUNTER; use work.PRIMS.all; architecture ALG of COUNTE is begin process (CLK) if CLK = ‘1’ then if RESET = ‘1’ then CNT<= “0000” after DEL; elsif LOAD = ‘1’ then CNT<= DATA_IN after DEL; elsif COUNT = ‘1’ then if UP = ‘1’ then CNT <= INC(CNT) after DEL; else CNT <= DEC(CNT) after DEL; end if; end process; end ALG; (fig. 4.37) Structured Logic Design with VHDL

Sequential Logic - Oscillator Primitive entity CLOCK_GENERATOR generic (PER:TIME); port (RUN: in BIT; CLK: out BIT); end CLOCK_GENERATOR; architecture ALG of CLOCK_GENERATOR is signal CLOCK:BIT; begin process (RUN,CLOCK) variable CLKE: BIT:=‘0’; if RUN=‘1’ and not RUN’STABLE then CLKE := ‘1’; CLOCK <= transport ‘0’ after PER/2; CLOCK <= transport ‘1’ after PER; end if; if RUN=‘0’ and not RUN’STABLE then CLKE:=‘0’; if CLOCK=‘1’ and not CLOCK’STABLE and CLKE=‘1’ then CLK <= CLOCK; end process; end ALG Necessary in any clocked sequential system. Example: oscillator with feedback delay. Feedback oscillator (fig 4.39) Structured Logic Design with VHDL

Sequential Logic - Oscillator Primitive entity COSC is generic (HI_TIME,LO_TIME: TIME); port (RUN: in BIT; CLOCK: out BIT:= ‘0’); end COSC; architecture ALG of COSC is begin process wait until RUN=‘1’; while RUN=‘1’ loop CLOCK <= ‘1’; wait for HI_TIME; CLOCK <= ‘0’; wait for LO_TIME; end loop; end process; end ALG; wait statement oscillator (fig. 4.40) Structured Logic Design with VHDL

Testing the Primitives Two common requirements for testing models: generation of clocks; generation of input combinations. Clock generation can be handled by oscillator primitives. Structured Logic Design with VHDL

Testing the Primitives entity PULSE_GEN is generic (N:INTEGER; PER:TIME); port (START: in BIT; PGOUT: out BIT_VECTOR(N-1 downto 0)); end PULSE_GEN; architecture ALG of PULSE_GEN is function INT_TO_BIN (INPUT: INTEGER; N: POSITIVE) return BIT_VECTOR is variable FOUT: BIT_VECTOR(0 to N-1); variable TEMP_A: INTEGER:= 0; variable TEMP_B: INTEGER:= 0; begin TEMP_A:= INPUT; for I in N-1 downto 0 loop TEMP_B:= TEMP_A/(2**I); TEMP_A:= TEMP_A rem (2**I); if (TEMP_B = 1)then FOUT(N-1-I):= ‘1’ else FOUT(N-1-I):= ‘0’; end if; end loop; return FOUT; end INT_TO_BIN; begin process (START) for I in 0 to 2**N-1 loop PGOUT<= transport INT_TO_BIN(I,N) after I*PER; end loop; end process; end ALG; Input combination generator (fig. 4.42) Structured Logic Design with VHDL

Literature: “Structured Logic Design With VHDL”
James R. Armstrong, F. Gail Gray; Virginia Tech Structured Design Concepts – entire chapter; Design Tools – recommended general information on pages ; Basic Features of VHDL – recommended entire chapter (pages ) with detailed examples and explanations; Basic VHDL Modeling Techniques – pages and Structured Logic Design with VHDL

STRUCTURED LOGIC DESIGN WITH VHDL

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