Divya Chiramana

• Designed and developed Class J power Amplifier to work at GHz range frequencies
• Tested the circuit in Agilent ADS. Used 0.35um CMOS technology
HBT Doherty Amplifier Design

• Designed and developed Doherty PA to work at 1.8 GHz frequency
• Did the Load pull measurement to find the matching
• Tested the circuit in Agilent ADS. Used GaAs HBT

Designed, Constructed and Tested Feb 2014 - April 2014
• Microstrip Resonator, Microwave Power Divider, Microwave Amplifier and Microwave Directional Coupler on FR-4 material
• Microstrip Filters on Duroid material and FR-4 material
• Octave-bandwidth feedback MMIC amplifier on GaAs
• A Microstrip patch antenna on Duroid material. Constructed a dipole antenna to detect and measure cell phone transmitted power

•Developed ALU code using Verilog behavioral code
•Constructed library of standard cells (inv, nand2, nor2, xor2, oa221, mux21 and dff) to convert Verilog behavioral code into netlist
•Automatic placement and routing of design was done using Cadence’s Encounter. Used IBM 130nm CMOS Technology


16 bit Customizable Microcontroller Design using Nexus 3 Spartan 6 Xilinx FPGA January 2014
• Implemented a 16 bit customizable microprocessor with 12 bit address bus that enables… Show more

•Developed ALU code using Verilog behavioral code
•Constructed library of standard cells (inv, nand2, nor2, xor2, oa221, mux21 and dff) to convert Verilog behavioral code into netlist
•Automatic placement and routing of design was done using Cadence’s Encounter. Used IBM 130nm CMOS Technology


16 bit Customizable Microcontroller Design using Nexus 3 Spartan 6 Xilinx FPGA January 2014
• Implemented a 16 bit customizable microprocessor with 12 bit address bus that enables access up to 4096 16-bit memory locations using Block RAM
• The design consists of basic microprocessor architecture with simple instruction consisting of four machine cycles
Programming Language: Verilog; Design Tools: Xilinx ISE, Adept Digilent 2.3.1; Hardware; Nexus 3 Spartan 6 Xilinx development platform.
Implementation of Ackermann Function using Nexus 3 Spartan 6 Xilinx FPGA
• Implemented Ackermann Function using LUT RAM synthesized at 60MHz
• Involved in synthesis, bit file generation and programming the FPGA with Digilent Adept.
Programming Language: Verilog; Design Tools: Xilinx ISE; Verification Tools: Adept Digilent 2.3.1; Hardware; Nexus 3 Spartan 6 Xilinx development platform.
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•Proposed and devised FMCW, multi-chirp, 8 receiver channel phased array radar
•Constructed satellite link to receive and transmit data regarding avalanches
•Tested radar and satellite link using AWR MWO

•Constructed LTE receiver for 3rd frequency band of spectrum which included designing of LNA, Mixer and Oscillator
•Tested the circuit simulation of entire receiver chain using Agilent ADS. Used 0.18um CMOS technology

A complete Cascode LNA design

• Calculated the values of passive components and transistor sizing to meet the project specifications using matlab.
• Using the calculated values, constructed the LNA in cadence using IBM 130nm CMOS technology
• 10%… Show more

•Constructed LTE receiver for 3rd frequency band of spectrum which included designing of LNA, Mixer and Oscillator
•Tested the circuit simulation of entire receiver chain using Agilent ADS. Used 0.18um CMOS technology

A complete Cascode LNA design

• Calculated the values of passive components and transistor sizing to meet the project specifications using matlab.
• Using the calculated values, constructed the LNA in cadence using IBM 130nm CMOS technology
• 10% variability of components is also checked. Full chip Layout of LNA is done including the bonding diagram and also considering the parasitics
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•Constructed Single stage Narrow Band Amplifier and 2 stage broadband amplifier
•The Circuit Simulations are done using AWR MWO. Trans Impedance gain simulations were done using MATLAB

• DISO Op-Amp was constructed to be used as a highly linear voltage buffer
• The schematic was tested using Cadence Circuit simulator. Used 0.25um CMOS technology

Designed MATLAB code that is able to automatically estimate the channel response and the corresponding poles and zeros for a given input and output sequences, and the code automatically generates an equalizer and estimates the input for any given output.

•Proposed the idea and computational algorithm for gesture recognition was implemented in Atmega 8 MCU
•Fabricated transmitter and receiver parts of working model. Have done final testing of the working model

•Researched on AES encryption method and developed Verilog code to encrypt data using AES
•Devised a method to improve AES system speed to encrypt data faster