EE 595

Part I
Introduction to VHDL

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 What is VHDL?

„ VHDL is a programming language that has been designed and

optimized for describing the behavior of digital circuits and
systems.

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 What is VHDL? (cont‘d)
„ VHDL (VHSIC (Very High Speed Integrated Circuits) Hardware
Description Language) is becoming increasingly popular as a
way to capture complex digital electronic circuit for both
simulation and synthesis.

„ Digital circuits captured using VHDL can be easily simulated,

and more likely to be synthesized into multiple target
technologies, and can be archived for later modification and
reuse.

„ VHDL is a rich and powerful language.

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 VHDL Language Features
„ VHDL has all the characteristics of a modern “programming”
language
„ Data types: predefined and user defined
„ Variables, Signals, and constants
„ Expressions: relational, logical, arithmetic, construction
„ Sequential Statements:
„ If, Case, For loop
„ Subprograms
„ Concurrent Statements:
„ Signal assignment, Concurrent processes, Component instances
„ Packages
„ Configurations
„ Dynamic memory allocation
„ File and input/output statements.

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 Additional Benefits of VHDL
„ Allows for various design methodologies
„ Provides technology independence
„ Describes a wide variety of digital hardware
„ Eases communication through standard
language
„ Allows for better design management
„ Provides a flexible design language
„ Has given rise to derivative standards: VITAL,
Analog VHDL
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 Goals of Language
„ Simulate-able specification for re-procurement
„ Standard format to exchange designs between
companies
„ Multi-vendor support
„ Support for huge designs
„ Determine behavior

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 VHDL Versus Programming
„ Designing in VHDL is like programming in many ways. Compiling and
running a VHDL design is similar to compiling and running other
programming languages. First, the source design units are read by the
compiler, error messages are given by analyzer, and an object module is
produced and placed in a special VHDL library. Subsequently, a
simulation run is made, in which the object units from a library are
selected (configured) and loaded into a simulator. A set of test cases are
run, either in batch or interactive mode. The main difference is that a
VHDL design is always running in simulated time, and events occur in
successive time steps.

Differences
Differences
• The notation of delay and the simulation environment Not common in
• Concurrency, and component netlisting } programming languages

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 VHDL Versus Programming
(cont’d)
A real hardware adder runs all the time, a design language needs a way of specifying
concurrent behavior (to represent the adder running in parallel with other simulated
hardware elements.) VHDL supports concurrency using the concept of concurrent
statements running in a simulation time; while concurrency is getting more
common, simulation time is a feature found only in simulation languages. In VHDL,
there are also sequential statements to describe algorithmic behavior.

Some programming languages provide for design hierarchy by having one main
Program and separately compiled subprograms. In VHDL, design hierarchy is
accomplished by separately compiled components that are instantiated in a higher-
level component. The linking process is done via the compiler, or by a simulator
using a VHDL library mechanism.

VHDL has a configuration capability for generating design variations.

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 VHDL History
„ Very High Speed Integrated Circuit (VHSIC) Program
„ Launched in 1980

„ Aggressive effort to advance state of the art

„ Object was to achieve significant gains in VLSI technology

„ Need for common descriptive language

„ $17 Million for direct VHDL development

„ $16 Million for VHDL design tools

„ Woods Hole Workshop

„ Held in June 1981 in Massachusetts

„ Discussion of VHSIC goals

„ Comprised of members of industry, government, and

academia

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 VHDL History (cont’d)
„ In July 1983, a team of Intermetrics, IBM and Texas
Instruments were awarded a contract to develop VHDL
„ In August 1985, the final version of the language under
government contract was released: VHDL Version 7.2
„ In December 1987, VHDL became IEEE Standard 1076-
1987 and in 1988 an ANSI standard
„ In September 1993, VHDL was restandardized to clarify
and enhance the language
„ VHDL has been accepted as a Draft International
Standard by the IEEE.

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 IEEE Standard 1076-1987
In 1986, the IEEE was presented with a proposal to standardize the
language, which it did in 1987 after substantial enhancements and
modifications were made by a team of commercial, government
and academic representatives. The resulting standard, IEEE 1076
-1987, is the basis for virtually every simulation and synthesis
product sold today. An enhanced and updated version of language,
IEEE 1076-1993, was released in 1994, and VHDL tool vendors
have been responding by adding these new language features to
Their products.

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 IEEE Standard 1164
„ Although IEEE standard 1076 defines the complete
VHDL language, there are aspects of the language
that make it difficult to write completely portable
design descriptions (descriptions that can be
simulated identically using different vendor’s tools).
z WHY? VHDL supports many abstract data types, but
does not directly address the problem of
characterizing different signal strengths or commonly
used simulation conditions such as unknowns and
high-impedance.

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 IEEE Standard 1164 (cont’d)
To get around this problem of non- standard data types,
another standard was developed by the committee and
adopted by the IEEE. This standard, numbered 1164,
defines a standard package (a VHDL feature that allows
commonly used declarations to be collected into an
external library) containing definitions for a standard nine-
valued data type. This standard data type is called
standard logic, and the IEEE 1164 package is often
referred to as the standard logic package, or sometimes
MVL9 (for multi-valued logic, nine values).

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 VITAL Initiative
„ The VITAL initiative (VHDL Initiative Toward ASIC
Libraries) effort to enhance VHDL’s abilities for modeling
timing in ASIC and FPGA design environments.
„ VITAL borrows liberally from existing methods for timing
annotation used in Verilog HDL. Specifically, the VITAL
standard (standard 1076.4)
„ Describes a method for annotating delay information using
the same underlying tabular format as specified in Verilog.
„ The adoptance of this standard will make it much easier
for ASIC and FPGA vendors to create timing-annotation
netlists and detailed behavior of devices.

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 Top Down Design
„ In Top-Down Design methodology, designer
represents a system abstractly at first, and later in
more detail.
„ A VHDL description can be written at various levels
of abstraction:
„ Algorithmic
„ Register Transfer Level (RTL)
„ Gate Level functional with unit delay(structural)
„ Gate Level with detailed timing

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 Top Down Design (cont’d)
VHDL provides ways of abstracting a design, or “hiding” implementation
details.

The algorithm can be evaluated in real(floating point), and later can be

Implemented in fixed-point integer.
(i.e. Designers often choose integers with 16 bits, but these
implementation decisions can be changed during a VHDL design cycle.)

In the previous example, addition is specified for 8-bit data. In actuality,

the + in this example might be a function call to user-written function called
plus (+). VHDL calls this technique operator overloading. Overloading is
another example of information hiding, which is convenient for the reader
and allows the design author to describe exactly what kind of operator is
wanted (+).

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 VHDL Design Steps
Design Description
in VHDL

Behavioral Identity requirements -

Simulation capacity & performance

RTL Level
Experiment with alternate functionality
Simulation

Experiment with alternate

Synthesizeable
implementations and verify function
RTL

Gate Level
Implementation

Gate Level Regression Test

Simulation

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 Simulation
„ A design description or model, written in VHDL, is usually run through a VHDL
simulator to demonstrate the behavior of the modeled system. Simulating a
VHDL design model requires simulated stimulus, a way of observing the model
during simulation, and capturing the results of simulation for later inspection.
Designer usually creates a set of test cases, for inputs and expected results, to
verify the function of the design. This file is called Testbench. For the previous
ADDER example, we would provide a set of functional test vectors as:

at
atsimulated
simulatedtime
time0:
0: B=
B=“0000
“00000010”
0010”
C=
C=“0000
“00000010”
0010”

„ The simulator would run to cover at least 5 ns of simulation time, and we could observe the output
on the A bus:
AA==“0000
“00000100”
0100”

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 Simulation (cont’d)
Logic simulator systems need to represent undefined or “unknown” values
for circuits with unresolved electrical values or states, which might be the
output of this circuit model during the first 4 ns of simulation time.
Accordingly, VHDL supports a variety of data types useful to the hardware
modeler for both simulation, and synthesis, as well as bits, booleans, and
numbers, which are defined in the Package STANDARD.

During simulation, the ADDER example is modeled on a computer

system, where the values on the busses are stored in the computer’s
memory. Hence, A, B, and C are similar to variables in programming
languages that change value over the time, and can be observed while the
program is running.

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 Logic Synthesis
Some parts of VHDL can be used with logic synthesis tools for producing a
physical design. In particular, many VLSI gate-array vendors can convert
a VHDL design description into a gate level netlist from which a
customized integrated circuit component can then be built. Hence the
application of VHDL is for:

• Documenting a design
• Simulating the behavior of a design
• Directly synthesizing logic

The ADDER is an abstraction of a real adder circuit, which might have

varying delays that are dependent upon the data, or on whether an output
rises or falls. Although a logic synthesis tool could generate an 8-bit adder
circuit, it could not produce an ideal adder with exactly 5.0 ns delay for all
cases. Only the addition function (not the delay specification) of the
statement in the example could be synthesized into a physical device.
(Delays and time specifications are ignored in Logic Synthesis.)

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